1. Field of the Invention
The invention relates to digital communication particularly with respect to decoding Manchester coded data.
2. Description of the Prior Art
Manchester coding is a popular data format for digital baseband communication. Manchester coding utilizes phase shift keying (PSK) to encode both clock and data into a single serial pulse stream. In the Manchester level or biphase level format (BPL), a transition occurs at the center of every data cell, the polarities thereof designating the binary data. This format utilizes a phase shift for each transistion between binary states. In such systems, a traditional format such as NRZ (non-return to zero) is encoded into Manchester, the Manchester code transmitted and the recovered Manchester code decoded back into NRZ. It is desirable in such systems, to incorporate the encoding and decoding circuitry into fully integrated circuits such as inexpensive digital gate array implementations. In traditional megahertz systems, encoders and decoders are known that operate at megahertz rates that are compatible with digital gate array implementation. Such conventional decoding techniques involve asynchronously sampling the Manchester code with a sampling clock running at a high multiple of the data rate. Traditionally, sampling may be effected at twelve times the data rate.
Another conventional decoding approach utilizes analog phase locked loop (PLL) circuitry. Phase locked loops tend to be complex and incompatible with digital standard cell or gate array implementation. Additionally, when utilizing PLL technology, a preamble or "leader" bits must precede a Manchester coded data transmission in order to phase lock the loop to the incoming data stream. In high frequency communication channels, especially linear buses, the preamble bits add significantly to the overhead costs of the channel, reducing the maximum possible data throughput.
With the advent of fiber optic communication channels, it has become possible to transmit information at extremely high data rates such as in the gigahertz range. The conventional digital decoding techniques, such as asynchronous sampling, fail to operate at these frequencies. For example, a fiber optic channel with a 1 gigahertz data rate, may require a 12 gigahertz sampling clock which is beyond the capabilities of available circuitry. Thus, in such high frequency applications, the phase locked loop is the only technology available for use as the decoding circuitry with the attendant disadvantages discussed above such as incompatibility with the fully integrated inexpensive digital gate array technology and the requirement of a preamble that undesirably loads the data bus.